Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices, including floating gate flash devices and charge trap flash (CTF) devices using semiconductor-oxide-nitride-oxide-semiconductor and metal-oxide-nitride-oxide-semiconductor capacitor structures that store information in charge traps in the nitride layer, may be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for sold state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players. Data, such as program code, user data, and/or system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This data may be used in personal computer systems, among others. Some uses of flash memory may include multiple reads of data programmed to a flash memory device without erasing the data.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to an access line, which is commonly referred to in the art, and herein, as a “word line.” However, each memory cell may not be directly coupled by its drain to a data line, which is commonly referred to in the art, and herein, as a “bit line.” Instead, the memory cells of the array may be coupled together in series, source to drain, between a common source and a data line, where the memory cells commonly coupled to a particular data line are referred to as a “column.”
Memory cells in a NAND array architecture may be programmed to a desired state. For example, electric charge can be placed on or removed from a charge storage node, such as a floating gate, of a memory cell to put the cell into one of a number of program states. For example, a single level cell (SLC) can represent two states, e.g., 1 or 0. Flash memory cells can also store more than two states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells may be referred to as multilevel cells (MLCs).
MLCs may allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one digit, e.g., more than one bit. For example, a cell capable of representing four digits can have sixteen program states. For some MLCs, one of the sixteen program states may be an erased state. For these MLCs, the lowermost program state is not programmed above the erased state, that is, if the cell is programmed to the lowermost state, it remains in the erased state rather than having a charge applied to the cell during a programming operation. The other fifteen program states may be referred to as “non-erased” states.
Two configurations used for programming memories are shielded and non-shielded. In non-shielded configurations, all bit line (ABL) programming can be used to simultaneously program all of the cells coupled to a particular access line, e.g., utilizing all bit lines. In shielded bit line (SBL) configurations, alternating memory cells on an access line can be programmed together, e.g., alternating bit lines are used. One or both bit lines adjacent to bit lines being programmed can be inhibited by application of an inhibit voltage.
ABL programming can provide faster programming operations compared to SBL programming, since all of the cells coupled to a particular access line can be programmed at the same time. However, in non-shielded configurations, capacitive coupling between memory cell components, e.g., components of adjacent memory cells, can have adverse effects on the memory cell being programmed. Memory cell components that may be capacitively coupled can include charge storage nodes, e.g., floating gates, channels, and bit lines, among others.